-- 4bit counter up/down with clear 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is   
port(clk,clr,up_down : in  std_logic;
     q : out std_logic_vector(3 downto 0));
    end counter;

architecture archi of counter is
   
signal tmp: std_logic_vector(3 downto 0);

begin     
process (clk,clr)       
begin         
        if (clr='1') then           
                  tmp<="0000";
  elsif (clk'event and clk='1') then
     if ( up_down='1') then
       tmp<=tmp+1;
	   else
	     tmp<=tmp-1;
	   end if;
	  end if;
end process;
	 q<=tmp;
	 end archi;