library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
  port(clock,reset : in std_logic;
  max_count        : in std_logic_vector(2 downto 0);
  count            : out std_logic_vector(2 downto 0));
end counter;

architecture behavior of counter is
    signal internal_count: STD_LOGIC_VECTOR(2 DOWNTO 0);
 BEGIN
   count<=internal_count;

   PROCESS(reset,clock)
  BEGIN
     IF reset='1' THEN
         internal_count<="000";
     ELSIF (CLOCK'event and CLOCK='1') then
       IF internal_count<max_count THEN
         internal_count<=internal_count+1;
     ELSE
         internal_count<="000";
       END IF;
     END IF;
 END PROCESS;
END behavior;