-- the name of the mane program is : my_ff.vhd 
-- Implementation of flip flop using NOR gates from package my_gates
-- this main program is using a package program name : my_gates.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.my_gates.ALL;

ENTITY my_ff IS
  PORT(set,reset: IN STD_LOGIC;
            q,nq: BUFFER STD_LOGIC);
END my_ff;

ARCHITECTURE use_package OF my_ff IS
BEGIN
  nor_1:my_nor PORT MAP(a => reset, b => nq,y => q);
  nor_2:my_nor PORT MAP(a => q, b => set,y => nq);
END use_package;

------------------------------------------------------------------------------------
my_gates.vhd
--package

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

PACKAGE my_gates IS
  COMPONENT my_nand
    PORT(a,b: IN STD_LOGIC;
           y: OUT STD_LOGIC);
  END COMPONENT;

  COMPONENT my_nor
    PORT(a,b: IN STD_LOGIC;
           y: OUT STD_LOGIC);
  END COMPONENT;
END my_gates;

   -- Implementation of my_nand
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY my_nand IS
  PORT(a,b :IN STD_LOGIC;
         y: OUT STD_LOGIC);
END my_nand;

ARCHITECTURE two_inputs OF my_nand IS
BEGIN
  y <= NOT (a AND b);
END two_inputs;
-----------------------------------------
   -- Implementation of my_nor
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY my_nor IS
  PORT(a,b :IN STD_LOGIC;
         y: OUT STD_LOGIC);
END my_nor;

ARCHITECTURE two_inputs OF my_nor IS
BEGIN
  y <= NOT (a OR b);
END two_inputs;